A Reconfigurable Multiplier Array For Video Image Processing Tasks, Suitable For Embedding In An FPGA Structure

Abstract This paper presents a design for a reconfigurable multiplier array. The multiplier is constructed using an array of 4 bit Flexible Array Blocks (FABs), which could be embedded within a conventional FPGA structure. The array can be configured to perform a number of 4n x 4m bit signed/unsigned binary multiplications. We have estimated that the FABs are about 35 times more efficient in area than the equivalent multiplier implemented using a conventional FPGA structure alone.

• Type: Conference
• Year: 1998
• Where: FCCM
• Authors: Simon D. Haynes, Peter Y. K. Cheung
• Keywords: Bit Flexible Array, Conventional Fpga Structure, FCCM 1998, Reconfigurable Multiplier Array, VLSI