: We investigated different parallel SIMD (single instruction multiple data) architectures based on pure programmable and reconfigurable approaches for their appropriateness for integration in an one chip high speed CMOS (complementary metal-oxide semiconductor) camera. Our goal is to combine parallel signal detection and parallel signal processing in one chip. By a logic synthesis we show that a reconfigurable combinatorial circuit based on morphological operations is superior for our purpose. Further we describe briefly how a such system can be expanded towards a self-organizing system.