Reconfigurable Shuffle Network Design in LDPC Decoders

Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the reconfigurability was seldom studied. In most of the published work, the shuffle network between the log-likelihood ratio (LLR) memory and the check- node units (CNU) is predetermined and optimized for a specific code. However, the most of the modern wireless communication systems typically specify multiple code-rates, codeword lengths and sub-matrix sizes (for the QC-LDPC codes) to provide and guarantee quality-of-service (QoS) over challenging channel conditions. It is therefore desirable to define a reconfigurable decoder architecture that can support different parameters. In this paper, we propose an adaptive shuffling algorithm for QC-LDPC codes which together with the Benes network provides arbitrary cyclic shift for arbitrary submatrix size smaller than the input size of the Benes network. For the submatrix size l...

• Type: Conference
• Year: 2006
• Where: ASAP
• Authors: Jun Tang, Tejas Bhatt, Vishwas Sundaramurthy
• Keywords: ASAP 2006, Benes Network, Hardware, Input Size, QC-LDPC Codes