A Reconfigurable Source-Synchronous On-Chip Network for GALS Many-Core Platforms

Abstract--This paper presents a GALS-compatible circuitswitched on-chip network that is well suited for use in many-core platforms targeting streaming DSP and embedded applications which typically have a high degree of task-level parallelism among computational kernels. Inter-processor communication is achieved through a simple yet effective reconfigurable sourcesynchronous network. Interconnect paths between processors can sustain a peak throughput of one word per cycle. A theoretical model is developed for analyzing the performance of the network. A 65 nm CMOS GALS chip utilizing this network was fabricated which contains 164 programmable processors, three accelerators and three shared memory modules. For evaluating the efficiency of this platform, a complete 802.11a WLAN baseband receiver was implemented. It has a real-time throughput of 54 Mbps with all processors running at 594 MHz and 0.95 V, and consumes an average of 174.8 mW with 12.2 mW (or 7.0%) dissipated by its interconnec...

• Type: Journal
• Year: 2010
• Where: TCAD
• Authors: Anh Thien Tran, Dean Nguyen Truong, Bevan M. Baas
• Keywords: Circuitswitched On-chip Network, Processors, Reconfigurable Sourcesynchronous Network, Software Engineering, TCAD 2010