High performance compilers increasingly rely on accurate modeling of the machine resources to efficiently exploit the instruction level parallelism of an application. In this paper, we propose a reducedmachinedescription thatresults in fasterdetectionof resource contentions while preserving the scheduling constraints present in the original machine description. The proposed approach reduces a machine description in an automated, error-free, and efficient fashion. Moreover, it fully supports schedulers that backtrack and processoperationsin arbitrary order. Reduceddescriptionsfor the DEC Alpha 21064,MIPS R3000/R3010,andCydra5 result in 4 to 7 times faster detection of resourcecontentionsand require 22 to 90% of the memory storage used by the original machine descriptions. Precise measurement for the Cydra 5 indicates that reducing the machine description results in a 2.9 times faster contention query module.
Alexandre E. Eichenberger, Edward S. Davidson