Reduced Z-datapath Cordic Rotator

In this article we propose a novel scheme based on virtually scaling-free COordinate Rotation DIgital Computer (CORDIC) algorithm to design a hardware efficient CORDIC rotator. For predicting rotation directions, less than 1/3rd of the elementary rotational stages require classical CORDIC iteration. The rest of the iteration directions could be computed in parallel and the corresponding z-datapath could be eliminated. A 16-bit implementation of the processor requires 0.23 mm2 silicon area and consumes 967.8 µW power when synthesized in 0.18 µm technology.

• Type: Conference
• Year: 2008
• Where: ISCAS
• Authors: Koushik Maharatna, Karim El-Shabrawy, Bashir M. Al-Hashimi
• Keywords: Classical Cordic Iteration, CORDIC, Efficient Cordic Rotator, Hardware, ISCAS 2008