Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization

Dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The delay and energy requirement of driving the result tags across the associatively-addressed issue queue accounts for a significant percentage of the scheduler’s overhead and also limits the design scalability. We propose two schemes to reduce the power consumption and the delays of the wakeup logic. Our first scheme – instruction packing – shares the associative part of an issue queue entry between two instructions, each with at most one non-ready source. As a result, the number of entries in the issue queue (and, hence, the length of the tag buses) can be reduced by a factor of two with almost no impact on the IPCs, because most instructions either enter the pipeline with at least one of their source operands ready, or do not make use of two source registers to begin with. Our second scheme – tag memoizatio...

• Type: Conference
• Year: 2004
• Where: PACS
• Authors: Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose, Oguz Ergin
• Keywords: Associatively-addressed Issue Queue, Hardware, Issue Queue, PACS 2004, Tag Buses