Redundant-Digit Floating-Point Addition Scheme Based on a Stored Rounding Value

—Due to the widespread use and inherent complexity of floating-point addition, much effort has been devoted to its speedup via algorithmic and circuit techniques. We propose a new redundant-digit representation for floating-point numbers that leads to computation speedup in two ways: 1) Reducing the per-operation latency when multiple floating-point additions are performed before result conversion to nonredundant format and 2) Removing the addition associated with rounding. While the first of these advantages is offered by other redundant representations, the second one is unique to our approach, which replaces the power- and area-intensive rounding addition by low-latency insertion of a rounding two-valued digit, or twit, in a position normally assigned to a redundant twit within the redundant-digit format. Instead of conventional sign-magnitude representation, we use a sign-embedded encoding that leads to lower hardware redundancy, and thus, reduced power dissipation. While our int...

• Type: Journal
• Year: 2010
• Where: TC
• Authors: Ghassem Jaberipur, Behrooz Parhami, Saeid Gorgin
• Keywords: Floating-point Additions, Information Technology, Multiple Floating-point Additions, Redundant Representation, TC 2010