A Register Allocation Technique Using Register Existence Graph

Optamzztng compalataon as very amportant for generatang code sequentes an order to utalaze the characterastacs of processor archatectures. One of the most essentaal optzmazataon technaques 1s regaster allocataon. In regaster allocataon that takes account of anstructaonlevel parallelasm, anta-dependences generated when the same regaster as allocated to dafferent varaables, and spall code generated when the number of regasters as ansuflczent should be handled an such a way that the parallelasm an a program as not lost. In our method, we realazed regaster allocatzon usang a new data structure called the regzster exzstence graph, an whzch the parallelasm zn a program as well expressed.

• Type: Conference
• Year: 1997
• Where: ICPP
• Authors: Akira Koseki, Yoshiaki Fukazawa, Hideaki Komatsu
• Keywords: 1s Regaster Allocataon, Distributed And Parallel Computing, Generatang Code, ICPP 1997, Processor Archatectures