Response compaction with any number of unknowns using a new LFSR architecture

This paper presents a new test response compaction technique with any number of unknown logic values (X’s) in the test response bits. The technique leverages an X-tolerant response compactor (X-compact), and forces X’s that are not tolerated by X-Compact to known values. The data required to designate the X’s not tolerated by the X-compactor, also called mask data, is stored in a compressed format on the tester and decompressed onchip. We applied this technique to four industrial designs and obtained 26-fold to 60-fold reduction in test response data volume with no impact on test quality. Categories and Subject Descriptors B.8.1 [Integrated Circuits]: Reliability, Testing, and Fault Tolerance. General Terms Algorithms, Design, Economics, Reliability, Theory. Keywords VLSI Test, Compression, X-compact, LFSR, BIST.

• Type: Conference
• Year: 2005
• Where: DAC
• Authors: Erik H. Volkerink, Subhasish Mitra
• Keywords: Computer Architecture, DAC 2005, Test Response, Test Response Bits, Test Response Compaction