REX - A VLSI Parasitic Extraction Tool for Electromigration and Signal Analysis

REX is a program that extracts parasitic resistance and capacitance values for nodes in VLSI layouts. REX also performs network serial and parallel simplifications. Two types of netlists are available, the SPICE-format for general purpose circuit simulation and a specially designed format for easy interface to internally developed analysis programs. The generated netlist contains information specifying where each resistor and capacitor is physically located in the original artwork. A graphical representation of the resistance and capacitance network is generated for overlaying with the mask layout for visual verification. REX is used in conjunction with a suite of analysis programs to perform engineering checks. Electromigration, power bus resistance, clock skew, noise analysis, and latch-up of CMOS VLSI chips are among the checks that utilize REX results.

• Type: Conference
• Year: 1991
• Where: DAC
• Authors: Jerry P. Hwang
• Keywords: Analysis Programs, CMOS VLSI Chips, Computer Architecture, DAC 1991, Power Bus Resistance