RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction

Inductance effects of on-chip interconnects have become more and more significant in today’s high-speed digital circuits, especially for global interconnects such as signal buses. However, most existing works consider only RC effects, e.g., the worst-case switching pattern resulting from coupling capacitance, to develop their encoding schemes to reduce bus delay. In this paper, we first show that the worst-case switching patterns that incur the largest bus delay are quite different while considering RC and RLC effects. The finding implies that existing encoding schemes based on the RC model might not improve or even worsen the bus delay when inductance effects become dominant. We then propose a bus-invert method to reduce the worst-case on-chip bus delay with the dominance of the inductance coupling effect. Simulation results show that our encoding method can significantly reduce the worst coupling delay of a bus.

• Type: Conference
• Year: 2005
• Where: ISCAS
• Authors: Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang
• Keywords: Bus Delay, Inductance Effects, ISCAS 2005, Worst-case Switching Patterns