Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival

A major trend in a modern system-on-chip design is a growing system complexity, which results in a sharp increase of communication traffic on the on-chip communication bus architectures. In a real-time embedded system, task arrival rate, inter-task arrival time, and data size to be transferred are not uniform over time. This is due to the partial re-configuration of an embedded system to cope with dynamic workload. In this context, the traditional application specific bus architectures may fail to meet the real-time constraints. Thus, to incorporate the random behavior of on-chip communication, this work proposes an approach to synthesize an on-chip bus architecture, which is robust for a given distributions of random tasks. The randomness of communication tasks is characterized by three main parameters which are the average task arrival rate, the average inter-task arrival time, and the data size. For synthesis, an on-chip bus requirement is guided by the worst-case performance need, ...

• Type: Conference
• Year: 2008
• Where: ASPDAC
• Authors: Sujan Pandey, Rolf Drechsler
• Keywords: ASPDAC 2008, Bus Architecture, Hardware, Inter-task Arrival Time, Task Arrival Rate