BLASTn is a ubiquitous tool used for large scale DNA analysis. Detailed profiling tests reveal that the most computationally intensive sections of the BLASTn algorithm are the scan and ungapped extension stages consuming approximately 94% of its total execution time. Exploiting the inherent parallel nature of an FPGA is the fundamental advantage of porting BLASTn onto it. The aim of this paper is two-fold. First, we build upon our prior work with BLAST to develop a hardware/software co-design that is composed of multiple cores that can be scaled in two dimensions. The ungapped extension and a second dimension are new in this work. Second, we use this non-trivial example to explore spatially scalable designs. To provide the ability to move the design to a future generation chip, a mathematical model of performance that incorporates all of the system design parameters and the user’s preference (high throughput vs low latency) is developed. We demonstrate here that the model correctly...