Scalable don't-care-based logic optimization and resynthesis

We describe an optimization method for combinational and sequential logic networks, with emphasis on scalability and the scope of optimization. The proposed resynthesis (a) is capable of substantial logic restructuring, (b) is customizable to solve a variety of optimization tasks, and (c) has reasonable runtime on industrial designs. The approach uses don’t cares computed for a window surrounding a node and can take into account external don’t cares (e.g. unreachable states). It uses a SAT solver and interpolation to find a new representation for a node. This representation can be in terms of inputs from other nodes in the window thus effecting Boolean re-substitution. Experimental results on 6-input LUT networks after high effort synthesis show substantial reductions in area and delay. When applied to 20 large academic benchmarks, the LUT count and logic level is reduced by 45.0% and 12.2%, respectively. The longest runtime for synthesis and mapping is about two minutes. When app...

• Type: Conference
• Year: 2009
• Where: FPGA
• Authors: Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Stephen Jang
• Keywords: 6-input Lut Networks, FPGA 2009, Hardware, Sequential Logic Networks, Substantial Logic Restructuring