Self Modifying Circuitry - A Platform for Tractable Virtual Circuitry

The readily available performance advantages, gained in early virtual circuitry systems, are being recouped following advances in general purpose processor architectures and have resulted in a questioning of the tractability of applying virtual circuitry in a general software environment. This paper highlights two primary limitations of existing virtual circuitry systems: technical bandwidth limitations, imposed by the use of a shared peripheral bus to interconnect the ble logic and host processor; and the abstract complications involved in traversing the hardware software divide within the inherently hardware software co-design environment of a virtual circuitry system. The Flexible URISC is introduced as an array resident minimal processor architecture with the potential to exploit self-reference and self-modi cation. Performance results of a prototype implementation of the Flexible URISC architecture demonstrate how peripheral bus bandwidth limitations are overcome by the increased...

• Type: Conference
• Year: 1998
• Where: FPL
• Authors: Adam Donlin
• Keywords: Flexible URISC, FPL 1998, Hardware, Hardware Software Divide, Virtual Circuitry System