SET and RESET pulse characterization in BJT-selected phase-change memories

- This paper presents program pulse characterization in an 8-Mb BJT-selected Phase-Change Memory test chip. Experimental results of the impact of the bit-line resistance over programming pulses efficiency are provided. Furthermore, in order to compensate for spreads in cell physical parameters in an array portion, a non-conventional staircase-down program pulse is proposed and experimentally evaluated.

• Type: Conference
• Year: 2005
• Where: ISCAS
• Authors: Ferdinando Bedeschi, Edoardo Bonizzoni, Giulio Casagrande, Roberto Gastaldi, Claudio Resta, Guido Torelli, Daniele Zella
• Keywords: ISCAS 2005, Program Pulse, Program Pulse Characterization, Staircase-down Program Pulse