This site uses cookies to deliver our services and to ensure you get the best experience. By continuing to use this site, you consent to our use of cookies and acknowledge that you have read and understand our Privacy Policy, Cookie Policy, and Terms
- This paper presents program pulse characterization in an 8-Mb BJT-selected Phase-Change Memory test chip. Experimental results of the impact of the bit-line resistance over programming pulses efficiency are provided. Furthermore, in order to compensate for spreads in cell physical parameters in an array portion, a non-conventional staircase-down program pulse is proposed and experimentally evaluated.
Ferdinando Bedeschi, Edoardo Bonizzoni, Giulio Cas