SEU Mitigation Techniques for Microprocessor Control Logic

The importance of fault tolerance at the processor architecture level has been made increasingly important due to rapid advancements in the design and usage of high performance devices and embedded processors. System level solutions to the challenge of fault tolerance flag errors and utilize penalty cycles to recover through the re-execution of instructions. This motivates the need for a hybrid technique providing fault detection as well as fault masking, with minimal penalty cycles for recovery from detected errors. We propose three architectural schemes to protect the control logic of microprocessors against Single Event Upsets (SEUs). High fault coverage with relatively low hardware overhead is obtained by using both fault detection with recovery and fault masking. Control signals are classified as either static or dynamic, and static signals are further classified as opcode dependent and instruction dependent. The strategy for protecting static instruction dependent control signal...

• Type: Conference
• Year: 2006
• Where: EDCC
• Authors: T. S. Ganesh, Viswanathan Subramanian, Arun K. Somani
• Keywords: Applied Computing, EDCC 2006, Fault Detection, Fault Masking, Fault Tolerance