Sign bit reduction encoding for low power applications

This paper proposes a low power technique, called SBR (Sign Bit Reduction) which may reduce the switching activity in multipliers as well as data buses. Utilizing the multipliers based on this scheme, the dynamic power consumption of some digital systems such as digital filters based on CMOS logic system can be reduced considerably compared to those based on 2’s complement implementation. To verify the efficacy of the SBR, a 16-bit multiplier was implemented by this scheme. The results for voice data show an average of 29% to 35% switching reduction compared to the 2’s complement implementation. For 16-bit random data, this scheme decreases the switching of 16-bit multipliers by an average of 21%. Finally, the application of the technique to a 16-bit data bus leads up to 14.5% switching reduction on average. Categories and Subject Descriptors B. Hardware B.2 ARITHMETIC AND LOGIC STRUCTURES General Terms Design Keywords Switching Activity, Low Power, Signed Multiplier, Bus Encoding...

• Type: Conference
• Year: 2005
• Where: DAC
• Authors: M. Saneei, Ali Afzali-Kusha, Zainalabedin Navabi
• Keywords: 16-bit Multipliers, Complement Implementation, Computer Architecture, DAC 2005, Switching Activity