Software-directed power-aware interconnection networks

Interconnection networks have been deployed as the communication fabric in a wide range of parallel computer systems. With recent technological trends allowing growing quantities of chip resources and faster clock rates, there have been prevailing concerns of increasing power consumption being a major limiting factor in the design of parallel computer systems, from multiprocessor SoCs to multi-chip embedded systems and parallel servers. To tackle this, power-aware networks must become inherent components of single-chip and multi-chip systems. On the hardware design side, while there has been some recent interconnection network power reduction research, especially targeted towards communication links, the techniques presented are ad hoc and are not tailored to the application running on the network. We show that with these ad hoc techniques, power savings and corresponding impact on network latency vary significantly from one application to the next – in many cases network performan...

• Type: Conference
• Year: 2005
• Where: CASES
• Authors: Vassos Soteriou, Noel Eisley, Li-Shiuan Peh
• Keywords: CASES 2005, Interconnection Network Power, Network Power, Parallelizing Compiler, System Software