On Some Implementation Issues for Value Prediction on Wide-Issue ILP Processors

In this paper, we look at two issues which could affect the performance of value prediction on wide-issue ILP processors. One is the large number of accesses to the value prediction tables needed in each machine cycle, and the other is the latency required to update stale values in the value prediction tables. We introduce a prediction value cache (PVC) which augments the instruction cache to hold the prediction values. Using the PVC, we not only can provide required bandwidth to access multiple prediction values needed in each machine cycle, but also allow us to decouple the value prediction fromthe critical path in the instruction fetch stage. We use a hybrid value predictor with dynamic classification to perform value prediction in the write back stage, and assume a realistic number of read/write ports, e.g. 2 read/write ports, with queues in their prediction tables. We found good performance for a 8 -issue processor using simulations. We also found that, in a 8-issue processor usi...

• Type: Conference
• Year: 2000
• Where: IEEEPACT
• Authors: Sang Jeong Lee, Pen-Chung Yew
• Keywords: Distributed And Parallel Computing, IEEEPACT 2000, Prediction Tables, Value Prediction Table, Value Predictions