A sparse VLIW instruction encoding scheme compatible with generic binaries

—Very Long Instruction Word (VLIW) processors are commonplace in embedded systems due to their inherent lowpower consumption as the instruction scheduling is performed by the compiler instead by sophisticated and power-hungry hardware instruction schedulers used in their RISC counterparts. This is achieved by maximizing resource utilization by only targeting a certain application domain. However, when the inherent application ILP (instruction-level parallelism) is low, resources are under-utilized/wasted and the encoding of NOPs results in large code sizes and consequently additional pressure on the memory subsystem to store these NOPs. To address the resource-utilization issue, we proposed a dynamic VLIW processor design that can merge unused resources to form additional cores to execute more threads. Therefore, the formation of cores can result in issue widths of 2, 4, and 8. Without sacrificing the possibility of code interruptability and resumption, we proposed a generic binary ...

• Type: Journal
• Year: 2015
• Where: RECONFIG
• Authors: Anthony Brandon, Joost Hoozemans, Jeroen van Straten, Arthur Francisco Lorenzon, Anderson Luiz Sartor, Antonio Carlos Schneider Beck, Stephan Wong
• Keywords: RECONFIG 2015, VLSI