SPR: an architecture-adaptive CGRA mapping tool

In this paper we present SPR, a new architecture-adaptive mapping tool for use with Coarse-Grained Reconfigurable Architectures (CGRAs). It combines a VLIW style scheduler and FPGA style placement and pipelined routing algorithms with novel mechanisms for integrating and adapting the algorithms to CGRAs. We introduce a latency padding technique that provides feedback from the placer to the scheduler to meet the constraints of a fixed frequency device with configurable interconnect. Using a new dynamic

• Type: Conference
• Year: 2009
• Where: FPGA
• Authors: Stephen Friedman, Allan Carroll, Brian Van Essen, Benjamin Ylvisaker, Carl Ebeling, Scott Hauck
• Keywords: Coarse-Grained Reconfigurable Architectures, FPGA 2009, FPGA Style Placement, Hardware, VLIW Style Scheduler