Standard CMOS technology on-chip inductors with pn junctions substrate isolation

New substrate isolation structures using pattern stacked pn junctions for on-chip inductors in standard CMOS technology are presented. For the first time, through increasing the reverse bias voltage to pn junctions, the lower substrate eddy loss due to the pn junction substrate isolation is reliably validated and the maximum quality factor is improved by 19%. The inductor without substrate shielding layer is compared to the inductor with metal one pattern ground shielding, pattern n-well, n+ diffusion, dual pn junctions isolation.

• Type: Conference
• Year: 2005
• Where: ASPDAC
• Authors: Hongyan Jian, Zhangwen Tang, Jie He, Jinglan He, Min Hao
• Keywords: ASPDAC 2005, Hardware, Pattern Stacked Pn, Pn Junctions, Substrate Isolation