State re-encoding for peak current minimization

In a synchronous finite state machine (FSM), huge current peaks are often observed at the moment of state transition. Previous low power state encoding algorithms focus on the reduction of switching activities of state registers (i.e., state bits). However, even though the switching state registers are the same, different combinations of switching directions still result in different peak currents. Based on that observation, in this paper, we propose the first approach to re-encode an FSM by considering the switching directions of state registers in order to minimize the peak current caused by the state transition. Experimental data consistently show that the peak current is reduced with no penalty. Categories and Subject Descriptors B.6.3 [Logic Design]: Design Aids – Optimization. General Terms Design, Reliability. Keywords Finite state machine, Peak current, Sequential circuit synthesis.

• Type: Conference
• Year: 2006
• Where: ICCAD
• Authors: Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh
• Keywords: Finite State Machine, Hardware, ICCAD 2006, State Registers, Synchronous Finite State