A study of the on-chip interconnection network for the IBM Cyclops64 multi-core architecture

The designs of high-performance processor architectures are moving toward the integration of a large number of multiple processing cores on a single chip. The IBM Cyclops-64 (C64) is a petaflop supercomputer built on multi-core system-on-a-chip technology. Each C64 chip employs a multistage pipelined crossbar switch as its on-chip interconnection network to provide high bandwidth and low latency communication between the 160 thread processing cores, the on-chip SRAM memory banks, and other components. In this paper, we present a study of the architecture and performance of the C64 on-chip interconnection network through simulation. Our experimental results provide observations on the network behavior: (1) Dedicated channels can be created between any output port to input port of the C64 crossbar with latency as low as 7 cycles. The C64 crossbar has the potential reach the full hardware bandwidth, and exhibit a non-blocking behavior; (2) The C64 crossbar is a stable network; (3) The n...

• Type: Conference
• Year: 2006
• Where: IPPS
• Authors: Yingping Zhang, Taikyeong Jeong, Fei Chen, Haiping Wu, R. Nitzsche, Guang R. Gao
• Keywords: C64 Crossbar, C64 On-chip Interconnection, Distributed And Parallel Computing, IPPS 2006, On-chip Interconnection Network