Synthesis of a Systolic Array Genetic Algorithm

The paper presents the design of a hardware genetic algorithm which uses a pipeline of systolic arrays. Demostrated is the design methodology, where a simple genetic algorithm expressed in C source code is progressivly re-written into a recurrence form from which systolic structures can be deduced. The paper extends previous work by the authors by introducing a simplification to a previous systolic design.

• Type: Conference
• Year: 1998
• Where: IPPS
• Authors: Graham M. Megson, I. M. Bland
• Keywords: Distributed And Parallel Computing, Genetic Algorithm, Hardware Genetic Algorithm, IPPS 1998, Systolic Arrays