Synthesis of Testable RTL Designs

With several commercial tools becoming available, the high-level synthesis of applicationspeci c integrated circuits is nding wide spread acceptance in VLSI industry today. Existing tools for synthesis focus on optimizing cost while meeting performance constraints or vice versa. Yet, veri cation and testing have emerged as major concerns of IC vendors since the repurcussions of chips being recalled are far-reaching. In this paper, we concentrate on the synthesis of testable RTL designs using techniques from Arti cial Intelligence. We present an adaptive version of the well known Simulated Annealing algorithm and describe its application to a combinatorial optimization problem arising in the high-level synthesis of digital systems. The conventional annealing algorithm was conceived with a single perturb operator which applies a small modi cation to the existing solution to derive a new solution. The Metropolis criterion is then used to accept or reject the new solution. In some of the ...

• Type: Conference
• Year: 1998
• Where: VLSID
• Authors: C. P. Ravikumar, Sumit Gupta, Akshay Jajoo
• Keywords: Adaptive Algorithms, Conventional Annealing Algorithm, Simulated Annealing Algorithm, VLSI, VLSID 1998