Synthesizing checkers for on-line verification of System-on-Chip designs

In modern System-on-Chip (SoC) designs verification becomes the major bottleneck. Since by using state-of-theart techniques complete designs cannot be fully formally verified, it becomes more and more important to check the correct behaviour during operation. This becomes even more significant in systems that are changed during lifetime, like re-configurable systems. In this paper we present a hardware extension that allows to efficiently synthesize checkers and properties that have been used in the verification process. This allows for an on-line verification of SoC designs. For the verification hardware a regular layout is discussed that can easily be synthesized and has a very low area overhead. The on-line check has (nearly) no effect on the delay of the considered chip.

• Type: Conference
• Year: 2003
• Where: ISCAS
• Authors: Rolf Drechsler
• Keywords: Designs Verification, ISCAS 2003, Major Bottleneck, Techniques Complete Designs