Synthesizing Iterative Functions into Delay-Insensitive Tree Circuits

Speed, cost and correctness may be the most important factors in designing a digital system. This paper proposes a novel and general methodology to synthesize iterative functions into potentially high speed, low cost and very robust circuits, called delay-insensitive combinational tree iterative circuits. In particular, our methodology can be applied to synthesize binary addition and comparison into delayinsensitive adders and comparators.

• Type: Conference
• Year: 1997
• Where: ICCD
• Authors: Fu-Chiung Cheng
• Keywords: Hardware, ICCD 1997, Iterative Functions, Robust Circuits, Tree Iterative Circuits