A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification

This paper provides a realistic case study of using the previously introduced SIMPPL system architectural model, which fixes the physical interface and communication protocols between processing elements (PEs) using PE-specific SIMPPL controllers. The implementation of a real-time MPEG-1 video decoder using SIMPPL provides a practical demonstration of how the complexity of system-level design issues are reduced by enabling rapid system-level integration and on-chip verification. The adaptation of the MPEG-1 PEs into the SIMPPL framework combined with the systemlevel integration was accomplished in 72.5 hours, which is only 4.5% of the overall system design time, instead of the more typical system integration times that can be as much as 30% of the design time.

• Type: Conference
• Year: 2006
• Where: FPL
• Authors: Lesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaña, Paul Chow
• Keywords: FPL 2006, Hardware, MPEG-1 Video Decoder, Rapid System-level Integration, System-level Design Issues