Systolic Architecture for Adaptive Censoring CFAR PI Detector

A new parallel algorithm for signal processing and a parallel systolic architecture of a robust constant false alarm rate (CFAR) processor with post-detection integration and adaptive censoring (RACPI) is presented in the paper. This detector is effective in conditions of flow from strong impulse interference. The ACPI CFAR processor uses sorting and censoring algorithms. We offer the sorting algorithm to be realized on the basis of the odd-even transposition sort method. We propose the censoring algorithm to be used for obtaining of the noise level estimation and for estimation of the impulse interference parameters. These parameters are needed for automatically choosing the scale factor, which keeps the false alarm rate constant. The real-time implementation of this detection algorithm requires large computational resources because of the great volume and high speed of the incoming data. The time consumption of the sorting and censoring procedures is also very high and therefore the...

• Type: Conference
• Year: 2005
• Where: LSSC
• Authors: Ivan Garvanov, Christo A. Kabakchiev, Plamen Daskalov
• Keywords: Censoring Algorithm, False Alarm Rate, LSSC 2005, Systolic Architecture