TELIOS: A Tool for the Automatic Generation of Logic Programming Machines

In this paper the tool TELIOS is presented, for the automatic generation of a hardware machine, corresponding to a given logic program. The machine is implemented using an FPGA, where a corresponding inference machine, in application specific hardware, is created on the FPGA, based on a BNF parser, to carry out the inference mechanism. The unification mechanism is based on actions embedded between the non-terminal symbols and implemented using special modules on the FPGA.

• Type: Journal
• Year: 2009
• Where: IFIP12
• Authors: Alexandros C. Dimopoulos, Christos Pavlatos, George K. Papakonstantinou
• Keywords: Application Specific Hardware, Corresponding Inference Machine, FPGA, IFIP12 2009, Information Technology