Test Pattern Generation for Signal Integrity Faults on Long Interconnects

In this paper, we present a test pattern generation algorithm aiming at signal integrity faults on long interconnects. This is achieved by considering the effect of inputs and parasitic RLC elements of the interconnect. To enhance the performance of test generation process, model order reduction methodology is employed. This strategy significantly improves the simulation time with slight loss of accuracy.

• Type: Conference
• Year: 2002
• Where: VTS
• Authors: Amir Attarha, Mehrdad Nourani
• Keywords: Parasitic Rlc Elements, Signal Integrity Faults, Test Pattern Generation, VLSI, VTS 2002