Testing of Uncustomized Segmented Channel Field Programmable Gate Arrays

This paper presents a methodology for production-time testing of (uncustomized) segmented channel eld programmable gate arrays (FPGAs) such as those manufactured by Actel [1]. The principles of this methodology are based on conguring the uncommitted modules (made of sequential and combinational logic circuits) of the FPGA as a set of disjoint one-dimensional arrays similar to iterative logic arrays (ILAs). These arrays can then be tested by establishing appropriate conditions such as constant testability (C-testability). A design approach is proposed. This approach is based on adding a small circuitry (consisting of two transistors) between each pair of uncustomized modules in a row for establishing the ILA conguration as a onedimensional unilateral array. It also requires the addition of a further primary pin. Features such as number of test vectors and hardware requirements (measured by the number of additional transistors and primary input/output pins) are analyzed; it is shown ...

• Type: Conference
• Year: 1995
• Where: FPGA
• Authors: Tong Liu, Wei-Kang Huang, Fabrizio Lombardi
• Keywords: Design Approach, Disjoint One-dimensional Arrays, FPGA, FPGA 1995