Thread clustering: sharing-aware scheduling on SMP-CMP-SMT multiprocessors

The major chip manufacturers have all introduced chip multiprocessing (CMP) and simultaneous multithreading (SMT) technology into their processing units. As a result, even low-end computing systems and game consoles have become shared memory multiprocessors with L1 and L2 cache sharing within a chip. Mid- and large-scale systems will have multiple processing chips and hence consist of an SMPCMP-SMT configuration with non-uniform data sharing overheads. Current operating system schedulers are not aware of these new cache organizations, and as a result, distribute threads across processors in a way that causes many unnecessary, long-latency cross-chip cache accesses. In this paper we describe the design and implementation of a scheme to schedule threads based on sharing patterns detected online using features of standard performance monitoring units (PMUs) available in today’s processing units. The primary advantage of using the PMU infrastructure is that it is fine-grained (down to...

• Type: Conference
• Year: 2007
• Where: EUROSYS
• Authors: David K. Tam, Reza Azimi, Michael Stumm
• Keywords: Cache Line, Cross-chip Cache Accesses, EUROSYS 2007, Performance Monitoring Units, System Software