Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors

With the shift towards chip multiprocessors (CMPs), exploiting and managing parallelism has become a central problem in computer systems. Many issues of parallelism management boil down to discerning which running threads or processes are critical, or slowest, versus which are non-critical. If one can accurately predict critical threads in a parallel program, then one can respond in a variety of ways. Possibilities include running the critical thread at a faster clock rate, performing load balancing techniques to offload work onto currently non-critical threads, or giving the critical thread more on-chip resources to execute faster. This paper proposes and evaluates simple but effective thread criticality predictors for parallel applications. We show that accurate predictors can be built using counters that are typically already available on-chip. Our predictor, based on memory hierarchy statistics, identifies thread criticality with an average accuracy of 93% across a range of arch...

• Type: Conference
• Year: 2009
• Where: ISCA
• Authors: Abhishek Bhattacharjee, Margaret Martonosi
• Keywords: Critical Thread, Criticality Prediction, Hardware, ISCA 2009, Thread Criticality