Per-thread cycle accounting in SMT processors

This paper proposes a cycle accounting architecture for Simultaneous Multithreading (SMT) processors that estimates the execution times for each of the threads had they been executed alone, while they are running simultaneously on the SMT processor. This is done by accounting each cycle to either a base, miss event or waiting cycle component during multi-threaded execution. Single-threaded alone execution time is then estimated as the sum of the base and miss event components; the waiting cycle component represents the lost cycle count due to SMT execution. The cycle accounting architecture incurs reasonable hardware cost (around 1KB of storage) and estimates single-threaded performance with average prediction errors around 7.2% for two-program work

• Type: Conference
• Year: 2009
• Where: ASPLOS
• Authors: Stijn Eyerman, Lieven Eeckhout
• Keywords: ASPLOS 2009, Cycle Accounting Architecture, Cycle Component, Lost Cycle Count, Programming Languages