Timing Driven Floorplanning on Programmable Hierarchical Targets

The goal of this paper is to perform a timing optimization of a circuit described by a network of cells on a target structure whose connection delays have discrete values following its hierarchy. The circuits is modelled by a set of timed cones whose delay histograms allow their classi cation into critical, potential critical and neutral cones according to predicted delays. The oorplanning is then guided by this cone structuring and has two innovative features: rst, it is shown that the placement of the elements of the neutral cones has no impact on timing results, thus a signi cant reduction is obtained; second, despite a greedy approach, a near optimal oorplan is achieved in a large number of examples.

• Type: Conference
• Year: 1998
• Where: FPGA
• Authors: S. A. Senouci, A. Amoura, Helena Krupnova, Gabriele Saucier
• Keywords: Connection Delays, FPGA, FPGA 1998, Neutral Cones, Timed Cones