Towards the logic defect diagnosis for partial-scan designs

Loical defect diagnosis is a critical yet challenging process in VLSI manufacturing. It involves the identification of the defect spots in a logic IC that fails testing. In the last decade, algorithms for diagnosis have progressed significantly and the results are showing promise for full-scan designs. In this paper, we will first review several classical algorithms such as fault dictionary based analysis and effect cause analysis. Then, we discuss several diagnosis algorithms borrowed from the design debugging techniques. These algorithms do not require a pre-determined fault model, and thus, are more flexible and applicable to ICs in which the defects do not behave like common stuck-at or bridging faults. Finally, we will probe the possibility of extending these algorithms to designs with only partial-scan support.

• Type: Conference
• Year: 2001
• Where: ASPDAC
• Authors: Shi-Yu Huang
• Keywords: Algorithms, ASPDAC 2001, Hardware, Loical Defect Diagnosis, Pre-determined Fault Model