Trading Conflict and Capacity Aliasing in Conditional Branch Predictors

As modern microprocessors employ deeper pipelines and issue multiple instructions per cycle, they are becoming increasingly dependent on accurate branch prediction. Because hardware resources for branch-predictor tables are invariably limited, it is not possible to hold all relevant branch history for all active branches at the same time, especially for large workloads consisting of multiple processes and operating-system code. The problem that results, commonly referred to as aliasing in the branch-predictor tables, is in many ways similar to the misses that occur in finite-sized hardware caches. In this paper we propose a new classification for branch aliasing based on the three-Cs model for caches, and show that conflict aliasing is a significant source of mispredictions. Unfortunately, the obvious method for removing conflicts

• Type: Conference
• Year: 1997
• Where: ISCA
• Authors: Pierre Michaud, André Seznec, Richard Uhlig
• Keywords: Aliasing, Branch-predictor Tables, Hardware, ISCA 1997, Skewed Branch Predictor