A Transformation-Based Approach for Storage Optimization

High-level synthesis (HLS) has been successfully targeted towards the digital signal processing (DSP) domain. Both application-specic integrated circuits (ASICs) and application-specic instruction-set processor (ASIPs) have been frequently designed using the HLS approach. Since most ASIP and DSP processors provide multiple addressing modes, and, in addition to classical constraint on the number of function units, registers, and buses, there are many resource usage rules, special considerations need to be paid to the optimizing code generation problem. In this paper we propose three transformation techniques, data management, data ordering, and transformational retiming, for storage optimization during code generation. With these transformations, some scheduling bottlenecks are eliminated, redundant instructions removed, and multiple operations mapped onto a single one. The proposed transformations have been implemented in a software system called Theda:MS. A set of benchmark program...

• Type: Conference
• Year: 1995
• Where: DAC
• Authors: Wei-Kai Cheng, Youn-Long Lin
• Keywords: Code Generation, Computer Architecture, DAC 1995, Dsp Processor, Multiple Addressing Modes