A triple port RAM based low power commutator architecture for a pipelined FFT processor

This paper proposes a low power commutator architecture based on triple port RAMs rather than dual port RAMs or conventional FIFO.forthe radix-4 pipelined FFTprocessor implementation. The triple port RAM based commutator consumes less power than the other two for the first and second stages of a 64-point radix-4 pipelined FFT processor. This commutator is attractive for shorter FFT’s but can also he used in the last stages of longer FIT’S.Up to 29% and 9% power savings is achieved for the 8-12 hit data range in the second and first stages of a 64-point F’FT processor respectively.

• Type: Conference
• Year: 2003
• Where: ISCAS
• Authors: M. Hasan, Tughrul Arslan
• Keywords: Commutator, ISCAS 2003, Low Power Commutator, Triple Port Ram