Ultra-low-power analog associative memory core using flash-EEPROM-based programmable capacitors

Analog techniques can lead to ultra-efficient computational systems when applied to the right applications. The problem of associative memory is well suited to array-based analog implementation. The architectures which result can be ultra efficient both in terms of high density and low power consumption. We have implemented a small (16x512) analog associative memory array which uses programmable nonlinear capacitors based on flash EEPROM technology for both analog storage and analog Manhattan Distance computation. The core circuit involved is based on only two of these novel devices. Preliminary results from this test circuit indicate that we can achieve a computing precision of more than 8 digitalequivalent bits in a chip which is capable of performing 128 Giga absolute-value-of-difference-accumulate operations per second at a power consumption of less than 150 mW. Performance of this level is more than an order of magnitude more efficient than the best low-power digital techniques a...

• Type: Conference
• Year: 1995
• Where: ISLPED
• Authors: Alan Kramer, Roberto Canegallo, Mauro Chinosi, D. Doise, Giovanni Gozzini, Pier Luigi Rolandi, M. Sabatini, P. Zabberoni
• Keywords: Analog, Analog Associative Memory, Analog Implementation, Hardware, ISLPED 1995