A unified methodology for power supply noise reduction in modern microarchitecture design

In this paper, we present a novel design methodology to combat the ever-aggravating high frequency power supply noise (di/dt) in modern microprocessors. Our methodology integrates microarchitectural profiling for noise-aware floorplanning, dynamic runtime noise control to prevent unsustainable noise emergencies, as well as decap allocation; all to produce a design for the average-case current consumption scenario. The dynamic controller contributes a microarchitectural technique to eliminate occurences of the worst-case noise scenario thus our method focuses on average-case noise behavior.

• Type: Conference
• Year: 2008
• Where: ASPDAC
• Authors: Michael B. Healy, Fayez Mohamood, Hsien-Hsin S. Lee, Sung Kyu Lim
• Keywords: ASPDAC 2008, Average-case Noise Behavior, Dynamic Runtime Noise, Hardware, Worst-case Noise Scenario