The use of carry-save representation in joint module selection and retiming

Joint module selection and retiming is a powerful technique to optimize the implementation cost and the speed of a circuit specified using a synchronous data-flow graph (DFG). In implementing high-speed circuits, the use of carry-save signal representation is also a powerful technique to optimize the implementation cost and the speed of arithmetic circuits. This paper is the first to combine these two techniques to solve the joint module selection and retiming problem while allowing the use of carry-save representation. To solve this problem efficiently, we first propose a mixedrepresentation data-flow graph (MFG) that allows signals to be expressed in carry-save representation. We also propose techniques to accurately model the costs associated with different signal representations. In addition, we propose a solution-space pruning technique that significantly reduces the run-time of our algorithm. Our algorithm, by allowing carry-save representation, can produce a wider range of solu...

• Type: Conference
• Year: 2000
• Where: DAC
• Authors: Zhan Yu, Kei-Yong Khoo, Alan N. Willson Jr.
• Keywords: DAC 2000, Design Automation, Joint Module Selection, Mixedrepresentation Data-flow Graph, Synchronous Data-flow Graph