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VTS
2000
IEEE
2000
IEEE
Using Arithmetic Transform for Verification of Datapath Circuits via Error Modeling
Real-time Traffic| Added | 26 Aug 2010 |
| Updated | 26 Aug 2010 |
| Type | Conference |
| Year | 2000 |
| Where | VTS |
| Authors | Katarzyna Radecka, Zeljko Zilic |
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