Using the DEVS Paradigm to Implement a Simulated Processor

This work is devoted to present the design and implementation of Alfa-1, a simulated computer with educational purposes. The DEVS formalism was used to attack the complexity of the design, allowing the definition of individual components that can be lately integrated into a modelling hierarchy. The tool is designed for the use in Computer Architecture and Organization courses. Its goal is allowing the students to acquire some practice in the design and implementation of hardware components by using simulation.

• Type: Conference
• Year: 2000
• Where: ANSS
• Authors: Sergio Daicz, Alejandro Troccoli, Sergio Zlotnik, Gabriel A. Wainer
• Keywords: ANSS 2000, DEVS Formalism, Educational Purposes, Modelling And Simulation, Modelling Hierarchy