On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization

The testing time for a system-on-chip (SOC) is determined to a large extent by the design of test wrappers and the test access mechanism (TAM). Wrapper/TAM co-optimization is therefore necessary for minimizing SOC testing time. We recently proposed an exact technique for co-optimization based on a combination of integer linear programming (ILP) and exhaustive enumeration. However, this approach is computationally expensive for large SOCs, and it is limited to fixed-width test buses. We present a new approach for wrapper/TAM co-optimization based on generalized rectangle packing, also referred to as two-dimensional packing. This approach allows us to decrease testing time by reducing the mismatch between a core’s test data needs and the width of the TAM to which it is assigned. We apply our co-optimization technique to an academic benchmark SOC and three industrial SOCs. Compared to the ILP-based technique, we obtain lower or comparable testing times for two out of the three industr...

• Type: Conference
• Year: 2002
• Where: VTS
• Authors: Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
• Keywords: SOC Testing Time, Testing Times, VLSI, VTS 2002, Wrapper/tam Co-optimization