Using Register Lifetime Predictions to Protect Register Files against Soft Errors

— Device scaling and large integration increase the vulnerability of microprocessors to transient errors. One of the structures where errors can be most harmful is the register file — a storage structure that is read very frequently. To increase the resistance of register files to soft errors, this paper presents the ParShield architecture. ParShield is based on two observations: (i) the data in a register is only useful for a small fraction of the register’s lifetime, and (ii) not all registers are equally vulnerable. ParShield selectively protects registers by generating, storing, and checking the ECCs of only the most vulnerable registers while they contain useful data. In addition, it stores a parity bit for all the registers, re-using the ECC circuitry for parity generation and checking. ParShield has no SDC AVF and a small average DUE AVF of 0.040 and 0.010 for the integer and floating-point register files, respectively. ParShield consumes on average only 81% and 78% of...

• Type: Conference
• Year: 2007
• Where: DSN
• Authors: Pablo Montesinos, Wei Liu, Josep Torrellas
• Keywords: Average Due Avf, Computer Networks, DSN 2007, Large Integration Increase, Register files